1. Technical Field
The present invention relates generally to semiconductor processing, and more particularly, to the formation of a capacitor and the capacitor so formed.
2. Related Art
A conventional method of producing a metal-insulator-metal capacitor using dual damascene processing is illustrated in related art FIGS. 1-5. In particular, FIG. 1 shows a structure 10 comprising a first metal wiring layer 11 and a second metal wiring layer 13. The first metal wiring layer 11 includes an insulative layer 12 having a first via 16 and a pair of first metal lines 18 formed therein. The second metal wiring layer 13 includes an insulative layer 14 having a plurality of second vias 20 and a second metal line 22 formed therein.
A capping layer 24, such as SiN, is deposited over the surface of the second metal wiring layer 13 to prevent the material within the second metal line 22 (typically copper), from oxidizing. A first mask (not shown) is used to pattern and etch an opening 26 within the capping layer 24 to expose the second vias 20 in the region where the capacitor is to be formed.
As shown in FIG. 2, a capacitor stack 28, comprising a first electrode layer 30, a dielectric layer 32 and a second electrode layer 34, is deposited over the surface of the second metal wiring layer 13. A second mask (not shown) is deposited over the capacitor stack 28 to pattern and etch the stack 28 as illustrated in FIG. 3. Following removal of the second mask, a third metal wiring layer 35 may be formed over the second metal wiring layer 13 by depositing an insulative layer 36, such as SiO2, over the structure 10 and planarizing the insulative layer 36. Thereafter, a plurality of third vias 38 and third metal lines 40 are formed in the insulative layer 36, as shown in FIG. 4.
However, there are several disadvantages associated with this method. For instance, because the second vias 20 and second metal lines 22 are typically formed of copper, which cannot be wire bonded, an additional metal wiring layer 35, having aluminum vias 38 and metal lines 40, must be formed over the capacitor stack 28 to make electrical connection.
The use of copper within the second vias 20 and second metal lines 22 also necessitates the use of a capping layer to prevent oxidation, as well as an additional masking step to form the capacitor stack opening in the capping layer 24. This creates additional steps which increase manufacturing time and costs.
Also, because the copper within the second metal line 22 and second vias 20 has a faster polish rate than the insulating material of the insulative layer 14, i.e., SiO2, xe2x80x9cdishingxe2x80x9d may occur. In other words, during a polishing step used to remove excess copper deposited to form the metal line 22 and vias 20, a portion of the exposed metal line 22 and second vias 20 is removed below the surface of the metal wiring layer 13, e.g., about 100-500 xc3x85, (FIG. 5). This creates corners 42 which are replicated in subsequent layers, e.g., the capping layer 24 and the capacitor stack 28. The thickness of the layers of the capacitor (30, 32, 34) will be reduced over the corners, particularly along the vertical sidewalls of the capacitor stack 28, and therefore, are more likely to cause device failures due to shorting.
In addition, the third vias 38 are simultaneously etched within the insulative layer 36. As illustrated in FIG. 4, the vias 38 over the capacitor 28 need to be etched to a depth less than that of the other vias 38. Therefore, the vias 38 and capacitor 28 are exposed a prolonged overetch. As a result, the capacitor 28 may be penetrated by the extended overetch, causing the capacitor 28 to be shorted out or damaged.
Furthermore, an additional step is required to planarize the material forming the third metal wiring layer 35 following deposition of the insulative layer 36 (typically, SiO2) because the capacitor stack 28 extends vertically above the capping layer 24, forming a bump or high spot within the insulative layer 36.
Therefore, there exists a need in the industry for a method of producing a metal-insulator-metal capacitor, using dual damascene processing, that overcomes these and other problems.
A first general aspect of the present invention provides a capacitor for a semiconductor device, comprising: a first and a second conductive element formed within a first insulative layer; a first conductive plate formed over the first conductive element; a second insulative layer formed over the first conductive plate; a second conductive plate formed over the second insulative layer; and a conductive layer electrically connecting the second conductive plate and the second conductive element.
A second general aspect of the present invention provides a semiconductor device, comprising: a first and a second conductive element formed within a first insulative layer; a capacitor formed over the first conductive element; a spacer formed around the capacitor; and a conductive layer electrically connecting the capacitor and the second conductive element.
A third general aspect of the present invention provides a method of forming a capacitor for a semiconductor device, comprising: forming at least a first and a second conductive element within an insulative layer; forming a capacitor over the first conductive element; forming a spacer around the capacitor; and forming a conductive layer electrically connecting the capacitor to the second conductive element.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of the embodiments of the invention.